The invention is directed to control systems, in general; and, in particular to a speed reference circuit for deployment with a control system suitable for directing a prime mover.
In a control system for a prime mover, a speed reference signal representing a desired prime mover speed is compared with a speed feedback signal representing an actual prime mover speed to produce an error signal representative of the lead or lag difference between the two signals which error is then used to direct corrective action in order to minimize the difference between the reference speed and the actual speed. There are numerous ways of introducing a reference signal including analog and digital circuitry. One analog system for introducing a reference signal simply comprises a mechanical dial which applies a voltage level equivalent to a desired speed to the circuit through a potentiometer or the equivalent thereof. Likewise, a digital reference signal could be input into a system by means of a variable control oscillator.
Circumstances may require that an input signal be available from a remote location such as a control room and a local site such as a panel adjacent the rotating machine. In the present invention such a dual panel arrangement is available and one aspect of the present invention is to provide priority logic so that the most appropriate reference signal is applied to the control system. The reference input signal is applied through either a remote or local keyboard. The input signal will either be an increase log or ramp; or, a decrease jog or ramp. The output of the priority logic is input into an an up-down counter through either an up count channel or a down count channel. The output of the up-down counter is then input into the speed control circuit of the prime mover.
During normal operation it is desirable to limit the applied reference signal to a range of standstill to high speed stop. This range is secured within the reference signal circuit by applying inhibit logic to the up count and down count channels respectively so that the inhibit logic is connected to the output of the up-down counter by means of signal feedback loops. Means are provided to override the high speed inhibit during the instance of overspeed test.
Reset circuitry and logic is provided so that the high speed inhibit is reset if an overspeed test is aborted and further reset provision is made to reset the up-down counter upon the occurrence of a turbine trip.